Custom 5-Stage MIPS CPU and FPGA Robotic Controller
Designed a 32-bit pipelined MIPS-like CPU in Verilog with hazard detection, forwarding, and a Wallace-tree multiplier, deployed on FPGA to control a custom walking robot.
Overview
Designed and implemented a 32-bit MIPS-like processor in Verilog featuring a classic five-stage pipeline (IF, ID, EX, MEM, WB). The processor includes a custom ALU, hazard detection unit, forwarding/bypassing logic, and hardware multiply/divide support. The CPU was deployed on a Xilinx Nexys A7 FPGA board and used as the compute core for a robotics project controlling a walking robot with fully custom mechanical linkages via memory-mapped motor controller peripherals.
Problem / Motivation
Building a pipelined processor introduces hazards that can break instruction ordering and correctness if not properly handled. The goal of the project was to design a fully functional pipelined CPU capable of executing assembly programs reliably while implementing hazard detection, forwarding, and hardware multiplication. The processor also needed to interface with external hardware through memory-mapped I/O in order to control a physical robotic system.
Technical Design
The CPU implements a 32-bit MIPS-like ISA using a five-stage pipeline consisting of instruction fetch, decode, execute, memory, and write-back stages. A custom ALU was designed to support arithmetic, logical, and comparison operations. Data hazards are resolved through a hazard detection unit combined with forwarding/bypass paths between pipeline stages to minimize stalls. A single-cycle Wallace-tree multiplier was implemented for high-speed multiplication within the execution stage. The processor interfaces with external peripherals through memory-mapped I/O registers, allowing assembly programs to control a motor controller used to drive the robot’s actuators. The system was implemented in Verilog, verified with simulation testbenches, and deployed to a Xilinx Nexys A7 FPGA board.
Key Challenges
- Designing pipeline control logic while ensuring correct handling of data and control hazards
- Implementing forwarding and bypass paths between pipeline stages to reduce stalls
- Integrating a single-cycle Wallace-tree multiplier into the execution stage
- Debugging pipeline behavior and instruction sequencing using waveform simulation
Results
- Successfully executed assembly test programs validating supported instructions
- Correctly handled pipeline hazards using forwarding and stall logic
- Deployed the CPU on a Xilinx Nexys A7 FPGA board as the control core for a walking robot